mzychla/RigolDSOPy
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

BH plot

Browse Source
This commit is contained in:
Zychlix 2026-04-07 11:24:58 +02:00
parent 5c5befacae
commit b4ebac4c25
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/rigol_dho_lib/rigol.py
View File

@ -26,7 +26,7 @@ class Channel:
self.scale_V = 5 self.scale_V = 5
self.setProbe(self.probe) self.setProbe(self.probe)
self.setVScale(self.scale_V) # self.setVScale(self.scale_V)
self.last_scale = 1 # V/div self.last_scale = 1 # V/div
@ -129,10 +129,14 @@ class Channel:
def clampVscale(self, val): def clampVscale(self, val):
if val > 100: if val > 100:
val = 100 val = 100
if val < 0.001: if val < 0.0001:
val = 0.001 val = 0.0001
return val return val
def getSpan(self): # display the difference between min and max voltage in dump
waveform = self.getWaveformRaw()
return np.max(waveform) - np.min(waveform)
class RigolOsc: class RigolOsc:
def __init__(self, visa_address: str): def __init__(self, visa_address: str):
@ -183,6 +187,7 @@ class RigolOsc:
def initialize(self): def initialize(self):
self.instr.write(":WAVeform:FORMat WORD") self.instr.write(":WAVeform:FORMat WORD")
self.instr.write(":WAVeform:MODE RAW") self.instr.write(":WAVeform:MODE RAW")
self.enable10MIn()
def getMemoryDepth(self): def getMemoryDepth(self):
@ -196,3 +201,6 @@ class RigolOsc:
def setTimescale(self, timebase: float): def setTimescale(self, timebase: float):
self.instr.write(f":TIMebase:MAIN:SCALe {timebase}") self.instr.write(f":TIMebase:MAIN:SCALe {timebase}")
def enable10MIn(self):
self.instr.write(":SYSTem:RCLock CINput")