From b4ebac4c25abd7af53e708f66a2fd21aecc9b2c9 Mon Sep 17 00:00:00 2001 From: Zychlix Date: Tue, 7 Apr 2026 11:24:58 +0200 Subject: [PATCH] BH plot --- src/rigol_dho_lib/rigol.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/rigol_dho_lib/rigol.py b/src/rigol_dho_lib/rigol.py index 0a7fb96..230b09e 100644 --- a/src/rigol_dho_lib/rigol.py +++ b/src/rigol_dho_lib/rigol.py @@ -26,7 +26,7 @@ class Channel: self.scale_V = 5 self.setProbe(self.probe) - self.setVScale(self.scale_V) + # self.setVScale(self.scale_V) self.last_scale = 1 # V/div @@ -129,10 +129,14 @@ class Channel: def clampVscale(self, val): if val > 100: val = 100 - if val < 0.001: - val = 0.001 + if val < 0.0001: + val = 0.0001 return val + def getSpan(self): # display the difference between min and max voltage in dump + waveform = self.getWaveformRaw() + return np.max(waveform) - np.min(waveform) + class RigolOsc: def __init__(self, visa_address: str): @@ -183,6 +187,7 @@ class RigolOsc: def initialize(self): self.instr.write(":WAVeform:FORMat WORD") self.instr.write(":WAVeform:MODE RAW") + self.enable10MIn() def getMemoryDepth(self): @@ -196,3 +201,6 @@ class RigolOsc: def setTimescale(self, timebase: float): self.instr.write(f":TIMebase:MAIN:SCALe {timebase}") + + def enable10MIn(self): + self.instr.write(":SYSTem:RCLock CINput")