From fbfd63849cf96b6a047bb2a0f0ee31e93b60d86a Mon Sep 17 00:00:00 2001
From: Zychlix <mzflighter@gmail.com>
Date: Fri, 10 Apr 2026 12:57:00 +0200
Subject: [PATCH] smieci

---
 src/rigol_dho_lib/rigol.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/rigol_dho_lib/rigol.py b/src/rigol_dho_lib/rigol.py
index 230b09e..0a4d498 100644
--- a/src/rigol_dho_lib/rigol.py
+++ b/src/rigol_dho_lib/rigol.py
@@ -26,7 +26,7 @@ class Channel:
         self.scale_V = 5
 
         self.setProbe(self.probe)
-        # self.setVScale(self.scale_V)
+        self.setVScale(self.scale_V)
 
         self.last_scale = 1  # V/div
 
@@ -129,8 +129,8 @@ class Channel:
     def clampVscale(self, val):
         if val > 100:
             val = 100
-        if val < 0.0001:
-            val = 0.0001
+        if val < 0.01:
+            val = 0.01
         return val
 
     def getSpan(self):  # display the difference between min and max voltage in dump